1. Field of the Invention
The present invention relates to a device for handling electronic signals of the type in which the signal level is represented by the difference between two input signals such that a well balanced output is achieved. This is useful in conversion to circuitry in which the signal level is represented by the absolute value of a signal with reference to power supply lines, and also for providing inputs to further differential type circuitry.
2. The Prior Art
In recent years there has been an increasing use of mixed bipolar/CMOS technologies in silicon integrated circuit design and manufacture. Also, the requirement for increased speed performance has led to the adoption of differential-type logic in some CMOS-only devices. (Current-mode logic (CML) and Emitter coupled logic (ECL) are both logic types in which a signal value is not represented by the absolute signal band on one line but rather by the difference, or the polarity of the difference, between the signal levels on a pair of lines. The term "differential-type logic" is used herein to refer to such arrangements.) In both of these cases there arises the need to convert the low-level differential signal from the differential-type logic into a full rail-to-rail signal for use with standard CMOS logic.
FIG. 1 is a schematic diagram of one previously known circuit for performing this type of conversion. The circuitry in FIG. 1 consists of a differential amplifier (Q1, Q2) with diode-connected PMOS loads (M1, M2). The differential input to the circuit (IPA, IPB) creates a current difference in the two PMOS loads which is mirrored in the second stage PMOS devices (M3, M5). The second stage uses a NMOS current mirror (M4, M6) as an active load to produce a large voltage swing at the circuit output (OPA). This circuit produces virtually a full rail-to rail signal at its output. However, the symmetry of the rising and falling output voltages tends to be poor due to the intrinsic asymmetry of the second stage: in effect the first stage differential amplifier output pulls OPA high through a single transistor (M5), whereas the pull-down is effected via three transistors (M3, M4 and M6).
An alternative design is shown in FIG. 2 and is based on a self-biased differential amplifier consisting of a differential pair (M1, M2) which uses a standard PMOS current mirror load (M5, M6). This current mirror bias voltage (VOB) is also used to set the operating current for this stage by controlling the gate of the two parallel current source transistors (M3, M4). The input stage generates a reasonably large swing at its output (VOA) which can then be applied directly to a CMOS inverter (M7, M8) to get a true CMOS level output (OPA). One advantage of this circuit is that by ratioing the gains of the devices such that:
.beta..sub.M1 =.beta..sub.M2 PA1 .beta..sub.MS =.beta..sub.M6 =K.beta..sub.M7 PA1 .beta..sub.M3 =.beta..sub.M4 =K.beta..sub.M8
the balance point of the differential amplifier stage can be made equal to the switching voltage of the output inverter. This consequently gives very good sensitivity to small signals. However, the signal swing of VOA around the balance point is rather asymmetrical and hence does not give well-balanced rise and fall times.
As mentioned, both of these two known converter circuits do not have good symmetry, that is the times taken to perform the two directions of switching operation differ, and this may mean that these converter devices cannot be used in situations where symmetry is important, for instance, in circuits where the timing of various signals is critical.
In differential-type logic circuits it is well known also to provide logic trees or arrays of transistors arranged to implement a defined logic function by combining one or more inputs to give an output. That output may be passed to further differential-type circuitry and for the best functioning of that further circuitry it is also important that the positive-going and negative-going transitions are symmetrical.
Alternatively the output from the logic function may require conversion to CMOS type signals and again, for the reasons discussed above, symmetry in the output is important.